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  • A low power computer to improve overall spacecraft performance

    Paper ID



    • H. Moffette Tharpe Jr.
    • David K. Sloper


    NASA, Goddard Space Flight Center






    A low-power digital computer for use on board scientific spacecraft is discussed. This computer utilizes a data bus to interconnect the CPU, the I/O and the memory units. Additional units may be added to the bus for expanded capability. The CPU is fully parallel, uses 2's complement arithmetic, has seven addressable registers, and adds in 6.25 microseconds. The I/O unit provides for inputting data in either a cycle steal or program-controlled mode and can handle sixteen interrupt levels. The proposed memory utilizes woven plated wire, ic-.-HDRO, and has a 2 microsecond cycle time. An English- like language has been developed to aid programming. An on-board central computer could be used to provide a unified spacecraft system. Such a computer could generate spacecraft or experiment commands, perform some on-board computations, increase slewing efficiency, or perform many operations now under ground control.